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Figures 2623 and 2624 show the architecture for a 3 Gbps pattern generator and error detector Because of the high bit rate, it is not practical to implement the PRBS and word generation directly in serial form Instead, the patterns are generated as parallel 16-bit words at a maximum rate of 200 Mbps, where shift registers and highcapacity memory can be implemented using bipolar technology (The high-speed circuitry normally would use gallium arsenide ICs) The high-speed multiplexer (using a pyramid of SPDT switches shown in Figure 2625) converts the parallel data to a serial stream at rates up to 3 Gbps

Another consideration in planning network connections is bandwidth availability in the area where the data center is located The required circuits may be easily ordered now, but what about in six months or a year It is vital that a company understands the capacity available, usually from the LEC, and its growth plans We have seen many customers experience delays in their entire data center build-outs because there were no additional circuits available from the LEC, and no one thought to check in advance (or they were overpromised by the LEC when they did enquire) TIP: It has been our experience over many years that telecommunication carriers are often overly optimistic when estimating the time required to install a circuit They are similarly overly optimistic about the time required to make an installed circuit work smoothly It is important to build extra time into the schedule for getting the circuit in and working Bandwidth Management Due to the nature of Internet Protocol traffic, any amount of network bandwidth can be swallowed up by a variety of both important and unimportant applications, with no respect to priority Thus, having the tools in place to manage, understand, report, and prioritize bandwidth is critical A discussion of tools for managing and prioritizing bandwidth is included in 6 of one of our previous books, Citrix Access Suite 4 for Windows Server 2003: The Official Guide

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PS (1) > $data = 1,2,3,4,5,6,7,8,9,10

Downloaded from Digital Engineering Library @ McGraw-Hill (wwwdigitalengineeringlibrarycom) Copyright 2004 The McGraw-Hill Companies All rights reserved Any use is subject to the Terms of Use as given at the website

Now convert them to a string:

Downloaded from Digital Engineering Library @ McGraw-Hill (wwwdigitalengineeringlibrarycom) Copyright 2004 The McGraw-Hill Companies All rights reserved Any use is subject to the Terms of Use as given at the website

4:

As an aside, variable expansion in strings goes through the same mechanism as the type converter, so you ll get the same result:

Figure 2625 Pyramidal multiplexer configuration Here, 16-bit data from the parallel gate array are fed to the first eight switches The output of these switches is fed to the next four switches and so on until a single serial data stream is generated The control of switch positions for each level is derived by dividing the clock rate by 2 at each stage

PS (3) > "$data" 1 2 3 4 5 6 7 8 9 10

The clock input is generated by a frequency synthesizer The clock output amplifier is driven through a fixed delay line, and the pattern generation and output amplifier are clocked through switched and vernier delay circuitry so that clock/data phase can be varied both positively and negatively The switched delays are 250, 500, and 1000 ps, while the vernier provides 0 to 250 ps in 1 ps increments The retimer associated with the output amplifier reclocks the data through a D-type flip-flop to maintain minimum jitter Since this type of test set normally would be used in a laboratory environment, the clock and data output levels and dc offsets can be varied for the particular application The companion error detector, shown in Figure 2624, uses a similar parallel implementation Clock and data inputs pass through fixed and vernier delays so that any arbitrary clock/data phase can be adjusted for optimal sampling in the error detector In fact, by adjusting the decision threshold and clock phasing under control of the internal processor, the error detector operating conditions can be optimized automatically The high-speed demultiplexer converts the serial data stream to 16bit parallel words along with a divide-by-16 clock signal The parallel implementation reference pattern generator synchronizes with the incoming data and makes a bitby-bit comparison Any errors that occur are counted by one of two counters One counter counts errors, while the other counter is being read in succession The measurement processor provides error performance analysis down to 1 ms resolution

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